Write a VHDL description to implement a simple counter state machine that counts from 0 to 15 and displays the current value of the counter on one of the seven-segment displays as a Hexadecimal number based on the following rules:
• If btnu is pressed, the counter will count up from its count value at a rate of 1 increment per 0.5 sec. If the maximum possible value (F) is reached the counter will stop counting.
• If btnd is pressed, the counter will count up from its count value at a rate of 1 increment per 0.5 sec. If the minimum possible value (0) is reached the counter will stop counting.
• If btnc is pressed (regardless of what btnu or butd are currently), the counter is (re)activated and the count value will display the 16-bit value of the board switched hex.
1) The state machine should also have a reset and clock inputs.
Note that each key may be pressed for multiple clock cycles, but each key press should be counted as just one input – that is, if the user presses and holds down a key for an extended time, it should be only counted as one key press.
2) Draw a complete state transition diagram for the state machine that will be included in your lab writeup. It may be hand drawn, but it must be readable, and neatness counts. Write a VHDL description that implements that state transition graph. Be sure to use an enumerated type for the state variables and use the 3-process description style shown in class.
3) Write a VHDL test bench that tests the counter state machine. The tests should include several input combinations. Be sure to trace all of the inputs and outputs to the state machine as well as the present state and next state variables and include the waveforms in your lab report – annotated to correspond to the descriptions of the tests in the test section of your report.
4) Write a structural “top_level” description that connects your state machine up to the proper signals in the FPGA. Note that you will need to use a clock divider to slow down the 100 MHz clock for your state machine to 0.5 Hz and a switch debouncer on each one of the inputs to the counter state machine. A schematic of how your state machine and the clock divider and switch debouncer should be connected is shown below. The top_level.vhd file provides a starting point for you to use. The Nexys4DDR_Master.xdc file might need to be adjusted to correspond to the top_level.vhd file.
5) Implement your design using the Xilinx Vivado toolset. Download the design into a Nexys4 board and test it for proper functionality.
6) Demonstrate your functioning counter state machine on the Nexsys4 board. You can do that by either 1) demonstrating the working design on the Nexsys4 board to the TA or the course instructor and have them signoff on the signoff sheet below, or 2) create a short video of you running your design on the Nexsys4 board where it functions correctly.
7) Turn in a full lab report as outlined in the course syllabus and the example lab writeup. Be sure to include a copy of your signoff sheet or a copy of your video. If you choose to submit a video, you must submit your solution as a zip file that contains both the PDF report and the video. The individual pages for your signoff sheet and your state transition diagram may be scanned and included in the PDF file.