This document is for Coventry University students for their own use in completing their
assessed work for this module and should not be passed to third parties or posted on any
website. Any infringements of this rule should be reported to
[email protected].
Faculty of Engineering, Environment and Computing
201CDE Module Title
Assignment Brief
Module Title
Analogue and Digital Electronics2
Individual Cohort (Sept) Module Code
201CDE
Coursework Title (e.g. CWK1)
Digital Coursework
Hand out date:
14th September 2020
Lecturer
Dr. Arfan Ghani
Due date and time:
23
rd October 2020
Moodle: 18:00:00
Estimated Time (hrs):
15
Word Limit*:
Coursework type:
Digital Design and
Implementation
% of Module Mark/
25%
Submission arrangement online via CUMoodle:
File types and method of recording: Submit through Aula as a pdf document naming the file name with
your student identification number as the file name
Mark and Feedback date:
Mark and Feedback method: Online
Module Learning Outcomes Assessed:
- Analyse and design synchronous sequential systems.
- Model digital systems for simulation and synthesis using an HDL.
Task and Mark distribution:
Marks breakdown Max Awarded
Sequential design and simulation 25
VHDL model and simulation 25
Assessor’s signature Total Total
50
This coursework involves the design and simulation of a synchronous sequential counter using a
traditional approach employing small scale logic components and a modern approach using
behavioural modelling with VHDL. The design specification for each student is unique and based on
their student ID number.
This document is for Coventry University students for their own use in completing their
assessed work for this module and should not be passed to third parties or posted on any
website. Any infringements of this rule should be reported to
[email protected].
Specification
Write down the seven digits of your student identification number below. An example is shown so
that you know what to expect.
Example
1 4 2 7 5 1 4
Actual SID
The digits in your ID number, in the right to left order are used to specify the sequential behaviour that a
synchronous counter will execute in response to applied clock pulses. Assume that the ID digits are
represented in a conventional 4-bit BCD code. The behaviour required of the counter is that it produces a 4-
bit digital output that represents the BCD value of the successive digits of your ID number in the right to left
sequence above. Once the left hand digit is output the counter will go back to the first and the sequence
repeats. Note the digits represent the outputs of the counter and not its state variables. - Traditional design
Draw a state diagram to represent the behaviour of the counter you are required to design. It is
suggested you employ the letters of the alphabet to refer to each state and keep the outputs as
decimal numbers at this stage.
➢
Insert state diagram here. (2 marks)
Convert the state diagram into its associated state table.
➢
Insert state table here. (2 marks)
Assume that a simple binary state variable allocation can be made and that any unused states can be
treated as don’t cares. Draw the corresponding transition table for the counter including flip-flop (DFF) inputs and BCD outputs for your designated storage device.
➢
Insert transition table here. (4 marks)
Using excitation maps (K-maps) to determine the next state logic functions that can be used to drive
your flip-flop inputs.
➢
Insert excitation maps clearly showing groups and logic functions here. (6 marks)
Also draw Karnaugh maps to deduce minimal logic functions for the 4 output functions that are
required to give the BCD output codes. Note that depending on your ID number not all outputs will
be significant in all cases.
➢
Insert the output function maps and logic equations here. (5 marks)
➢
Enter the associated schematic circuit diagram here along with commentary. The simulation
results clearly show the implementation is fully compliant with the specification. (6 marks)
This document is for Coventry University students for their own use in completing their
assessed work for this module and should not be passed to third parties or posted on any
website. Any infringements of this rule should be reported to
[email protected]. - VHDL Design
For exactly the same counter specification in Part 1, write a VHDL entity and architecture that will
model the required sequential behaviour. The VHDL code should be entered in a VHDL tool such
as Xilinx Vivado to confirm that it compiles without errors.
➢
Insert your VHDL model design with proof of compilation here. (9 marks)
Also write a test bench that will enable the correct function of the counter model to be simulated.
Again include proof that it compiles without errors on your design tool.
➢
Insert your VHDL test bench here. (8 marks)
➢
Finally include output from the simulator that confirms your design simulates correctly.
Briefly explain why you consider the result gives this confirmation. Insert simulation results
and commentary here. (8 marks)
Note: it is very important that the work submitted is an individual effort. The penalties for
plagiarism are severe.
Notes: - You are expected to use the Coventry University Harvard Referencing Style. For support and
advice on this students can contact Centre for Academic Writing (CAW). - Please notify your registry course support team and module leader for disability support.
- Any student requiring an extension or deferral should follow the university process as outlined
here. - The University cannot take responsibility for any coursework lost or corrupted on disks, laptops
or personal computer. Students should therefore regularly back-up any work and are advised to
save it on the University system. - If there are technical or performance issues that prevent students submitting coursework
through the online coursework submission system on the day of a coursework deadline, an
appropriate extension to the coursework submission deadline will be agreed. This extension will
normally be 24 hours or the next working day if the deadline falls on a Friday or over the
weekend period. This will be communicated via your Module Leader. - You are encouraged to check the originality of your work by using the draft Turnitin links on your
Moodle Web. - Collusion between students (where sections of your work are similar to the work submitted by
other students in this or previous module cohorts) is taken extremely seriously and will be
reported to the academic conduct panel. This applies to both courseworks and exam answers. - A marked difference between your writing style, knowledge and skill level demonstrated in class
discussion, any test conditions and that demonstrated in a coursework assignment may result in
you having to undertake a Viva Voce in order to prove the coursework assignment is entirely your
own work.
This document is for Coventry University students for their own use in completing their
assessed work for this module and should not be passed to third parties or posted on any
website. Any infringements of this rule should be reported to
[email protected]. - If you make use of the services of a proof reader in your work you must keep your original version
and make it available as a demonstration of your written efforts. - You must not submit work for assessment that you have already submitted (partially or in full),
either for your current course or for another qualification of this university, unless this is
specifically provided for in your assignment brief or specific course or module information. Where
earlier work by you is citable, ie. it has already been published/submitted, you must reference it
clearly. Identical pieces of work submitted concurrently will also be considered to be selfplagiarism.
Mark allocation guidelines to students (to be edited by staff per assessment)
0-39 40-49 50-59 60-69 70+ 80+
Work mainly
incomplete
and /or
weaknesses in
most areas
Most elements
completed;
weaknesses
outweigh
strengths
Most elements
are strong,
minor
weaknesses
Strengths in all
elements
Most work
exceeds the
standard
expected
All work
substantially
exceeds the
standard
expected